/*
module divider_kch(
	iClk, // input clock
	iReset, // reset signal
	iReady, // indicates inputs are ready
	oDone, // indicates that the result is ready
	iDividend, // 16-bit dividende [15:0]
	iDivisor, // 8-bit multiplicand [7:0]
	oQuotient, // 8-bit quotient [15:0]
	oReminder, // 8-bit reminder [7:0]
	);

input iClk;
input iReset;
input iReady;
input [15:0] iDividend;
input [7:0] iDivisor;

output [15:0] oQuotient;
output [7:0] oReminder;
output oDone;


wire r;
wire [7:0] divisor;

and f(r,iReset,iReady);
*/
module divider_kch(
	iClk, // input clock
	iReset, // reset signal
	iReady, // indicates inputs are ready
	oDone, // indicates that the result is ready
	iDividend, // 16-bit dividende [15:0]
	iDivisor, // 8-bit multiplicand [7:0]
	oQuotient, // 8-bit quotient [15:0]
	oReminder, // 8-bit reminder [7:0]
	);

input iClk;
input iReset;
input iReady;
input [15:0] iDividend;
input [7:0] iDivisor;

output [15:0] oQuotient;
output [7:0] oReminder;
output oDone;


wire r;
wire [7:0] divisor;

and f(r,iReset,iReady);

//module register_16bit(clk,rst,d,q);
wire [7:0] SA;
wire [7:0] SA_;
wire [15:0] SQ;

and e1(SA[0],iDividend[15],1);
and e2(SA[1],iDividend[15],1);
and e3(SA[2],iDividend[15],1);
and e4(SA[3],iDividend[15],1);
and e5(SA[4],iDividend[15],1);
and e6(SA[5],iDividend[15],1);
and e7(SA[6],iDividend[15],1);
and e8(SA[7],iDividend[15],1);


register_24bit divd(iClk,r,{SA,iDividend},{SA_,SQ});
register_8bit divs(iClk,r,iDivisor,divisor);


/////////////////start/////////////////


////////////////1 term/////////////////

wire [7:0] A_1;
wire [7:0] A__1;

wire [15:0] Q_1;
wire [15:0] Q__1;

term t1(SA_,SQ,A_1,A__1,Q_1,Q__1,divisor);

////////////////2 term/////////////////

wire [7:0] A_2;
wire [7:0] A__2;

wire [15:0] Q_2;
wire [15:0] Q__2;


term t2(A__1,Q__1,A_2,A__2,Q_2,Q__2,divisor);


////////////////3 term/////////////////

wire [7:0] A_3;
wire [7:0] A__3;

wire [15:0] Q_3;
wire [15:0] Q__3;

term t3(A__2,Q__2,A_3,A__3,Q_3,Q__3,divisor);

////////////////4 term/////////////////

wire [7:0] A_4;
wire [7:0] A__4;

wire [15:0] Q_4;
wire [15:0] Q__4;

term t4(A__3,Q__3,A_4,A__4,Q_4,Q__4,divisor);

////////////////5 term/////////////////

wire [7:0] A_5;
wire [7:0] A__5;

wire [15:0] Q_5;
wire [15:0] Q__5;

term t5(A__4,Q__4,A_5,A__5,Q_5,Q__5,divisor);

////////////////6 term/////////////////

wire [7:0] A_6;
wire [7:0] A__6;

wire [15:0] Q_6;
wire [15:0] Q__6;

term t6(A__5,Q__5,A_6,A__6,Q_6,Q__6,divisor);

////////////////7 term/////////////////

wire [7:0] A_7;
wire [7:0] A__7;

wire [15:0] Q_7;
wire [15:0] Q__7;

term t7(A__6,Q__6,A_7,A__7,Q_7,Q__7,divisor);

////////////////8 term/////////////////

wire [7:0] A_8;
wire [7:0] A__8;

wire [15:0] Q_8;
wire [15:0] Q__8;

term t8(A__7,Q__7,A_8,A__8,Q_8,Q__8,divisor);

////////////////9 term/////////////////

wire [7:0] A_9;
wire [7:0] A__9;

wire [15:0] Q_9;
wire [15:0] Q__9;

term t9(A__8,Q__8,A_9,A__9,Q_9,Q__9,divisor);

////////////////10 term/////////////////

wire [7:0] A_10;
wire [7:0] A__10;

wire [15:0] Q_10;
wire [15:0] Q__10;

term t10(A__9,Q__9,A_10,A__10,Q_10,Q__10,divisor);

////////////////11 term/////////////////

wire [7:0] A_11;
wire [7:0] A__11;

wire [15:0] Q_11;
wire [15:0] Q__11;

term t11(A__10,Q__10,A_11,A__11,Q_11,Q__11,divisor);

////////////////12 term/////////////////

wire [7:0] A_12;
wire [7:0] A__12;

wire [15:0] Q_12;
wire [15:0] Q__12;

term t12(A__11,Q__11,A_12,A__12,Q_12,Q__12,divisor);


////////////////13 term/////////////////

wire [7:0] A_13;
wire [7:0] A__13;

wire [15:0] Q_13;
wire [15:0] Q__13;

term t13(A__12,Q__12,A_13,A__13,Q_13,Q__13,divisor);

////////////////14 term/////////////////

wire [7:0] A_14;
wire [7:0] A__14;

wire [15:0] Q_14;
wire [15:0] Q__14;

term t14(A__13,Q__13,A_14,A__14,Q_14,Q__14,divisor);

////////////////15 term/////////////////

wire [7:0] A_15;
wire [7:0] A__15;

wire [15:0] Q_15;
wire [15:0] Q__15;

term t15(A__14,Q__14,A_15,A__15,Q_15,Q__15,divisor);

////////////////16 term/////////////////

wire [7:0] A_16;
wire [7:0] A__16;

wire [15:0] Q_16;
wire [15:0] Q__16;

term t16(A__15,Q__15,A_16,A__16,Q_16,Q__16,divisor);


wire [7:0] oRe;
wire [15:0] oQu;


///////////////compare sign of dividend and divisor -> 2nd complement of Quotient

wire p;
wire s;

xor p0(s,iDividend[15],divisor[7]);

add_sub_16bit p1(oQu,p,0,Q__16,s);


/////////////////////////////////////////////////////////////////////////////////

assign oRe[7]=A__16[7];
assign oRe[6]=A__16[6];
assign oRe[5]=A__16[5];
assign oRe[4]=A__16[4];
assign oRe[3]=A__16[3];
assign oRe[2]=A__16[2];
assign oRe[1]=A__16[1];
assign oRe[0]=A__16[0];

register_8bit re(iClk,r,oRe,oReminder);
register_16bit qu(iClk,r,oQu,oQuotient);

wire [1:0] fi;

or finish(fi[0],oQuotient[0],oQuotient[1],oQuotient[2],oQuotient[3],oQuotient[4],oQuotient[5],oQuotient[6],oQuotient[7],
		oQuotient[8],oQuotient[9],oQuotient[10],oQuotient[11],oQuotient[12],oQuotient[13],oQuotient[14],oQuotient[15]);

and fin(fi[1],fi[0],r);
assign oDone=fi[1];

endmodule

module mux_2to1(s,in,out);

input s;
input [1:0] in;
output out;
wire a,b,c;

not q1(a,s);
and q2(b,in[0],a);
and q3(c,in[1],s);
or q4(out,b,c);  // s=0 -> in[0]  s=1 -> in[1]

endmodule

module left_shift(in,out);

input [23:0] in;
output [23:0] out;

or or1(out[0],0,0);
or or2(out[1],in[0],0);
or or3(out[2],in[1],0);
or or4(out[3],in[2],0);
or or5(out[4],in[3],0);
or or6(out[5],in[4],0);
or or7(out[6],in[5],0);
or or8(out[7],in[6],0);
or or9(out[8],in[7],0);
or or10(out[9],in[8],0);
or or11(out[10],in[9],0);
or or12(out[11],in[10],0);
or or13(out[12],in[11],0);
or or14(out[13],in[12],0);
or or15(out[14],in[13],0);
or or16(out[15],in[14],0);
or or17(out[16],in[15],0);
or or18(out[17],in[16],0);
or or19(out[18],in[17],0);
or or20(out[19],in[18],0);
or or21(out[20],in[19],0);
or or22(out[21],in[20],0);
or or23(out[22],in[21],0);
or or24(out[23],in[22],0);



endmodule

module full_adder(out,cout,in1,in2,cin);

input in1;
input in2;
input cin;
output out;
output cout;

wire w1,w2,w3;

xor t1(w1,in1,in2);
xor t2(out,w1,cin);
and t3(w2,in1,in2);
and t4(w3,w1,cin);
or  t6(cout,w2,w3);

endmodule


module add_sub_8bit(out,cout,in1,in2,M);

input [7:0] in1;
input [7:0] in2;
input M; //M=0 add M=1 sub

output [7:0] out;
output cout ;

wire [7:0] w1,w2;

xor x1(w1[0],M,in2[0]);
xor x2(w1[1],M,in2[1]);
xor x3(w1[2],M,in2[2]);
xor x4(w1[3],M,in2[3]);
xor x5(w1[4],M,in2[4]);
xor x6(w1[5],M,in2[5]);
xor x7(w1[6],M,in2[6]);
xor x8(w1[7],M,in2[7]);

full_adder f1(out[0],w2[0],in1[0],w1[0],M);
full_adder f2(out[1],w2[1],in1[1],w1[1],w2[0]);
full_adder f3(out[2],w2[2],in1[2],w1[2],w2[1]);
full_adder f4(out[3],w2[3],in1[3],w1[3],w2[2]);
full_adder f5(out[4],w2[4],in1[4],w1[4],w2[3]);
full_adder f6(out[5],w2[5],in1[5],w1[5],w2[4]);
full_adder f7(out[6],w2[6],in1[6],w1[6],w2[5]);
full_adder f8(out[7],w2[7],in1[7],w1[7],w2[6]);


endmodule

module add_sub_16bit(out,cout,in1,in2,M);

input [15:0] in1;
input [15:0] in2;
input M; //M=0 add M=1 sub

output [15:0] out;
output cout ;

wire [15:0] w1,w2;

xor x1(w1[0],M,in2[0]);
xor x2(w1[1],M,in2[1]);
xor x3(w1[2],M,in2[2]);
xor x4(w1[3],M,in2[3]);
xor x5(w1[4],M,in2[4]);
xor x6(w1[5],M,in2[5]);
xor x7(w1[6],M,in2[6]);
xor x8(w1[7],M,in2[7]);
xor x9(w1[8],M,in2[8]);
xor x10(w1[9],M,in2[9]);
xor x11(w1[10],M,in2[10]);
xor x12(w1[11],M,in2[11]);
xor x13(w1[12],M,in2[12]);
xor x14(w1[13],M,in2[13]);
xor x15(w1[14],M,in2[14]);
xor x16(w1[15],M,in2[15]);

full_adder f1(out[0],w2[0],in1[0],w1[0],M);
full_adder f2(out[1],w2[1],in1[1],w1[1],w2[0]);
full_adder f3(out[2],w2[2],in1[2],w1[2],w2[1]);
full_adder f4(out[3],w2[3],in1[3],w1[3],w2[2]);
full_adder f5(out[4],w2[4],in1[4],w1[4],w2[3]);
full_adder f6(out[5],w2[5],in1[5],w1[5],w2[4]);
full_adder f7(out[6],w2[6],in1[6],w1[6],w2[5]);
full_adder f8(out[7],w2[7],in1[7],w1[7],w2[6]);
full_adder f9(out[8],w2[8],in1[8],w1[8],w2[7]);
full_adder f10(out[9],w2[9],in1[9],w1[9],w2[8]);
full_adder f11(out[10],w2[10],in1[10],w1[10],w2[9]);
full_adder f12(out[11],w2[11],in1[11],w1[11],w2[10]);
full_adder f13(out[12],w2[12],in1[12],w1[12],w2[11]);
full_adder f14(out[13],w2[13],in1[13],w1[13],w2[12]);
full_adder f15(out[14],w2[14],in1[14],w1[14],w2[13]);
full_adder f16(out[15],w2[15],in1[15],w1[15],w2[14]);


endmodule

module dflipflop(
  clk,
  rst, 
  input1,
  output1,
  noutput1
);

input input1, clk, rst;
output output1, noutput1;

wire w1, w2, w3, w4;
wire  input2;
and a1(input2, input1, rst);

nand n1(w1, w4, w2);
nand n2(w2, w1, clk);
nand n3(w3, w2, clk, w4);
nand n4(w4, w3, input2);

nand n5(output1, w2, noutput1);
nand n6(noutput1, output1, w3);


endmodule

module register_8bit(clk,rst,d,q);

  input clk, rst;
  input [7:0]d;
  output [7:0]q;
  
  wire [7:0]nq;
  
  dflipflop d1(clk, rst, d[0], q[0], nq[0]);
  dflipflop d2(clk, rst, d[1], q[1], nq[1]);
  dflipflop d3(clk, rst, d[2], q[2], nq[2]);
  dflipflop d4(clk, rst, d[3], q[3], nq[3]);
  dflipflop d5(clk, rst, d[4], q[4], nq[4]);
  dflipflop d6(clk, rst, d[5], q[5], nq[5]);
  dflipflop d7(clk, rst, d[6], q[6], nq[6]);
  dflipflop d8(clk, rst, d[7], q[7], nq[7]);
  
endmodule
  
module register_16bit(clk,rst,d,q);
  
input clk, rst;
input [15:0]d;
output [15:0]q;

register_8bit er1(clk, rst, d[15:8], q[15:8]);
register_8bit er2(clk, rst, d[7:0], q[7:0]);

endmodule

module register_24bit(clk,rst,d,q);
  
input clk, rst;
input [23:0]d;
output [23:0]q;

register_8bit er1(clk, rst, d[23:16], q[23:16]);
register_8bit er2(clk, rst, d[15:8], q[15:8]);
register_8bit er3(clk, rst, d[7:0], q[7:0]);


endmodule

module term(BA_,BQ_,A_,A__,Q_,Q__,divi);

input [7:0] BA_;
input [15:0] BQ_;


input [7:0] A_;
output [7:0] A__;

input [15:0] Q_;
output [15:0] Q__;

input [7:0] divi; 

wire [7:0] X_;

wire [3:0] s_; 		// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_;

left_shift l({BA_,BQ_},{A_,Q_});

xnor x01(s_[0],A_[7],divi[7]);

add_sub_8bit a0(X_,c_,A_,divi,s_[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x02(s_[1],A_[7],X_[7]);

or x03(s_[2],X_[7],X_[6],X_[5],X_[4],X_[3],X_[2],X_[1],X_[0]);

and x04(s_[3],s_[2],s_[1]);

mux_2to1 m01(s_[3],{A_[0],X_[0]},A__[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m02(s_[3],{A_[1],X_[1]},A__[1]);
mux_2to1 m03(s_[3],{A_[2],X_[2]},A__[2]);
mux_2to1 m04(s_[3],{A_[3],X_[3]},A__[3]);
mux_2to1 m05(s_[3],{A_[4],X_[4]},A__[4]);
mux_2to1 m06(s_[3],{A_[5],X_[5]},A__[5]);
mux_2to1 m07(s_[3],{A_[6],X_[6]},A__[6]);
mux_2to1 m08(s_[3],{A_[7],X_[7]},A__[7]);

not o01(Q__[0],s_[3]);
or o02(Q__[1],0,Q_[1]);
or o03(Q__[2],0,Q_[2]);
or o04(Q__[3],0,Q_[3]);
or o05(Q__[4],0,Q_[4]);
or o06(Q__[5],0,Q_[5]);
or o07(Q__[6],0,Q_[6]);
or o08(Q__[7],0,Q_[7]);
or o09(Q__[8],0,Q_[8]);
or o010(Q__[9],0,Q_[9]);
or o011(Q__[10],0,Q_[10]);
or o012(Q__[11],0,Q_[11]);
or o013(Q__[12],0,Q_[12]);
or o014(Q__[13],0,Q_[13]);
or o015(Q__[14],0,Q_[14]);
or o016(Q__[15],0,Q_[15]);

endmodule













/*
//module register_16bit(clk,rst,d,q);
wire [7:0] SA;
wire [7:0] SQ;
register_16bit divd(iClk,r,iDividend,{SA,SQ});
register_8bit divs(iClk,r,iDivisor,divisor);


/////////////////start/////////////////


////////////////1 term/////////////////

wire [7:0] A_1;
wire [7:0] A__1;

wire [7:0] Q_1;
wire [7:0] Q__1;

wire [7:0] X_1;

wire [3:0] s_1; 	// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_1;

left_shift l1({SA,SQ},{A_1,Q_1});

xnor x11(s_1[0],A_1[7],divisor[7]);

add_sub_8bit a1(X_1,c_1,A_1,divisor,s_1[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x12(s_1[1],A_1[7],X_1[7]);

or x13(s_1[2],X_1[7],X_1[6],X_1[5],X_1[4],X_1[3],X_1[2],X_1[1],X_1[0]);

and x14(s_1[3],s_1[2],s_1[1]);

mux_2to1 m11(s_1[3],{A_1[0],X_1[0]},A__1[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m12(s_1[3],{A_1[1],X_1[1]},A__1[1]);
mux_2to1 m13(s_1[3],{A_1[2],X_1[2]},A__1[2]);
mux_2to1 m14(s_1[3],{A_1[3],X_1[3]},A__1[3]);
mux_2to1 m15(s_1[3],{A_1[4],X_1[4]},A__1[4]);
mux_2to1 m16(s_1[3],{A_1[5],X_1[5]},A__1[5]);
mux_2to1 m17(s_1[3],{A_1[6],X_1[6]},A__1[6]);
mux_2to1 m18(s_1[3],{A_1[7],X_1[7]},A__1[7]);

not o11(Q__1[0],s_1[3]);
or o12(Q__1[1],0,Q_1[1]);
or o13(Q__1[2],0,Q_1[2]);
or o14(Q__1[3],0,Q_1[3]);
or o15(Q__1[4],0,Q_1[4]);
or o16(Q__1[5],0,Q_1[5]);
or o17(Q__1[6],0,Q_1[6]);
or o18(Q__1[7],0,Q_1[7]);

////////////////2 term/////////////////

wire [7:0] A_2;
wire [7:0] A__2;

wire [7:0] Q_2;
wire [7:0] Q__2;

wire [7:0] X_2;

wire [3:0] s_2; 	// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_2;

left_shift l2({A__1,Q__1},{A_2,Q_2});

xnor x21(s_2[0],A_2[7],divisor[7]);

add_sub_8bit a2(X_2,c_2,A_2,divisor,s_2[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x22(s_2[1],A_2[7],X_2[7]);

or x23(s_2[2],X_2[7],X_2[6],X_2[5],X_2[4],X_2[3],X_2[2],X_2[1],X_2[0]);

and x24(s_2[3],s_2[2],s_2[1]);

mux_2to1 m21(s_2[3],{A_2[0],X_2[0]},A__2[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m22(s_2[3],{A_2[1],X_2[1]},A__2[1]);
mux_2to1 m23(s_2[3],{A_2[2],X_2[2]},A__2[2]);
mux_2to1 m24(s_2[3],{A_2[3],X_2[3]},A__2[3]);
mux_2to1 m25(s_2[3],{A_2[4],X_2[4]},A__2[4]);
mux_2to1 m26(s_2[3],{A_2[5],X_2[5]},A__2[5]);
mux_2to1 m27(s_2[3],{A_2[6],X_2[6]},A__2[6]);
mux_2to1 m28(s_2[3],{A_2[7],X_2[7]},A__2[7]);

not o21(Q__2[0],s_2[3]);
or o22(Q__2[1],0,Q_2[1]);
or o23(Q__2[2],0,Q_2[2]);
or o24(Q__2[3],0,Q_2[3]);
or o25(Q__2[4],0,Q_2[4]);
or o26(Q__2[5],0,Q_2[5]);
or o27(Q__2[6],0,Q_2[6]);
or o28(Q__2[7],0,Q_2[7]);

////////////////3 term/////////////////

wire [7:0] A_3;
wire [7:0] A__3;

wire [7:0] Q_3;
wire [7:0] Q__3;

wire [7:0] X_3;

wire [3:0] s_3; 	// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_3;

left_shift l3({A__2,Q__2},{A_3,Q_3});

xnor x31(s_3[0],A_3[7],divisor[7]);

add_sub_8bit a3(X_3,c_3,A_3,divisor,s_3[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x32(s_3[1],A_3[7],X_3[7]);

or x33(s_3[2],X_3[7],X_3[6],X_3[5],X_3[4],X_3[3],X_3[2],X_3[1],X_3[0]);

and x34(s_3[3],s_3[2],s_3[1]);

mux_2to1 m31(s_3[3],{A_3[0],X_3[0]},A__3[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m32(s_3[3],{A_3[1],X_3[1]},A__3[1]);
mux_2to1 m33(s_3[3],{A_3[2],X_3[2]},A__3[2]);
mux_2to1 m34(s_3[3],{A_3[3],X_3[3]},A__3[3]);
mux_2to1 m35(s_3[3],{A_3[4],X_3[4]},A__3[4]);
mux_2to1 m36(s_3[3],{A_3[5],X_3[5]},A__3[5]);
mux_2to1 m37(s_3[3],{A_3[6],X_3[6]},A__3[6]);
mux_2to1 m38(s_3[3],{A_3[7],X_3[7]},A__3[7]);

not o31(Q__3[0],s_3[3]);
or o32(Q__3[1],0,Q_3[1]);
or o33(Q__3[2],0,Q_3[2]);
or o34(Q__3[3],0,Q_3[3]);
or o35(Q__3[4],0,Q_3[4]);
or o36(Q__3[5],0,Q_3[5]);
or o37(Q__3[6],0,Q_3[6]);
or o38(Q__3[7],0,Q_3[7]);

////////////////4 term/////////////////

wire [7:0] A_4;
wire [7:0] A__4;

wire [7:0] Q_4;
wire [7:0] Q__4;

wire [7:0] X_4;

wire [3:0] s_4; 	// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_4;

left_shift l4({A__3,Q__3},{A_4,Q_4});

xnor x41(s_4[0],A_4[7],divisor[7]);

add_sub_8bit a4(X_4,c_4,A_4,divisor,s_4[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x42(s_4[1],A_4[7],X_4[7]);

or x43(s_4[2],X_4[7],X_4[6],X_4[5],X_4[4],X_4[3],X_4[2],X_4[1],X_4[0]);

and x44(s_4[3],s_4[2],s_4[1]);

mux_2to1 m41(s_4[3],{A_4[0],X_4[0]},A__4[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m42(s_4[3],{A_4[1],X_4[1]},A__4[1]);
mux_2to1 m43(s_4[3],{A_4[2],X_4[2]},A__4[2]);
mux_2to1 m44(s_4[3],{A_4[3],X_4[3]},A__4[3]);
mux_2to1 m45(s_4[3],{A_4[4],X_4[4]},A__4[4]);
mux_2to1 m46(s_4[3],{A_4[5],X_4[5]},A__4[5]);
mux_2to1 m47(s_4[3],{A_4[6],X_4[6]},A__4[6]);
mux_2to1 m48(s_4[3],{A_4[7],X_4[7]},A__4[7]);

not o41(Q__4[0],s_4[3]);
or o42(Q__4[1],0,Q_4[1]);
or o43(Q__4[2],0,Q_4[2]);
or o44(Q__4[3],0,Q_4[3]);
or o45(Q__4[4],0,Q_4[4]);
or o46(Q__4[5],0,Q_4[5]);
or o47(Q__4[6],0,Q_4[6]);
or o48(Q__4[7],0,Q_4[7]);

////////////////5 term/////////////////

wire [7:0] A_5;
wire [7:0] A__5;

wire [7:0] Q_5;
wire [7:0] Q__5;

wire [7:0] X_5;

wire [3:0] s_5; 	// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_5;

left_shift l5({A__4,Q__4},{A_5,Q_5});

xnor x51(s_5[0],A_5[7],divisor[7]);

add_sub_8bit a5(X_5,c_5,A_5,divisor,s_5[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x52(s_5[1],A_5[7],X_5[7]);

or x53(s_5[2],X_5[7],X_5[6],X_5[5],X_5[4],X_5[3],X_5[2],X_5[1],X_5[0]);

and x54(s_5[3],s_5[2],s_5[1]);

mux_2to1 m51(s_5[3],{A_5[0],X_5[0]},A__5[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m52(s_5[3],{A_5[1],X_5[1]},A__5[1]);
mux_2to1 m53(s_5[3],{A_5[2],X_5[2]},A__5[2]);
mux_2to1 m54(s_5[3],{A_5[3],X_5[3]},A__5[3]);
mux_2to1 m55(s_5[3],{A_5[4],X_5[4]},A__5[4]);
mux_2to1 m56(s_5[3],{A_5[5],X_5[5]},A__5[5]);
mux_2to1 m57(s_5[3],{A_5[6],X_5[6]},A__5[6]);
mux_2to1 m58(s_5[3],{A_5[7],X_5[7]},A__5[7]);

not o51(Q__5[0],s_5[3]);
or o52(Q__5[1],0,Q_5[1]);
or o53(Q__5[2],0,Q_5[2]);
or o54(Q__5[3],0,Q_5[3]);
or o55(Q__5[4],0,Q_5[4]);
or o56(Q__5[5],0,Q_5[5]);
or o57(Q__5[6],0,Q_5[6]);
or o58(Q__5[7],0,Q_5[7]);

////////////////6 term/////////////////

wire [7:0] A_6;
wire [7:0] A__6;

wire [7:0] Q_6;
wire [7:0] Q__6;

wire [7:0] X_6;

wire [3:0] s_6; 	// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_6;

left_shift l6({A__5,Q__5},{A_6,Q_6});

xnor x61(s_6[0],A_6[7],divisor[7]);

add_sub_8bit a6(X_6,c_6,A_6,divisor,s_6[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x62(s_6[1],A_6[7],X_6[7]);

or x63(s_6[2],X_6[7],X_6[6],X_6[5],X_6[4],X_6[3],X_6[2],X_6[1],X_6[0]);

and x64(s_6[3],s_6[2],s_6[1]);

mux_2to1 m61(s_6[3],{A_6[0],X_6[0]},A__6[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m62(s_6[3],{A_6[1],X_6[1]},A__6[1]);
mux_2to1 m63(s_6[3],{A_6[2],X_6[2]},A__6[2]);
mux_2to1 m64(s_6[3],{A_6[3],X_6[3]},A__6[3]);
mux_2to1 m65(s_6[3],{A_6[4],X_6[4]},A__6[4]);
mux_2to1 m66(s_6[3],{A_6[5],X_6[5]},A__6[5]);
mux_2to1 m67(s_6[3],{A_6[6],X_6[6]},A__6[6]);
mux_2to1 m68(s_6[3],{A_6[7],X_6[7]},A__6[7]);

not o61(Q__6[0],s_6[3]);
or o62(Q__6[1],0,Q_6[1]);
or o63(Q__6[2],0,Q_6[2]);
or o64(Q__6[3],0,Q_6[3]);
or o65(Q__6[4],0,Q_6[4]);
or o66(Q__6[5],0,Q_6[5]);
or o67(Q__6[6],0,Q_6[6]);
or o68(Q__6[7],0,Q_6[7]);

////////////////7 term/////////////////

wire [7:0] A_7;
wire [7:0] A__7;

wire [7:0] Q_7;
wire [7:0] Q__7;

wire [7:0] X_7;

wire [3:0] s_7; 	// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_7;

left_shift l7({A__6,Q__6},{A_7,Q_7});

xnor x71(s_7[0],A_7[7],divisor[7]);

add_sub_8bit a7(X_7,c_7,A_7,divisor,s_7[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x72(s_7[1],A_7[7],X_7[7]);

or x73(s_7[2],X_7[7],X_7[6],X_7[5],X_7[4],X_7[3],X_7[2],X_7[1],X_7[0]);

and x74(s_7[3],s_7[2],s_7[1]);

mux_2to1 m71(s_7[3],{A_7[0],X_7[0]},A__7[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m72(s_7[3],{A_7[1],X_7[1]},A__7[1]);
mux_2to1 m73(s_7[3],{A_7[2],X_7[2]},A__7[2]);
mux_2to1 m74(s_7[3],{A_7[3],X_7[3]},A__7[3]);
mux_2to1 m75(s_7[3],{A_7[4],X_7[4]},A__7[4]);
mux_2to1 m76(s_7[3],{A_7[5],X_7[5]},A__7[5]);
mux_2to1 m77(s_7[3],{A_7[6],X_7[6]},A__7[6]);
mux_2to1 m78(s_7[3],{A_7[7],X_7[7]},A__7[7]);

not o71(Q__7[0],s_7[3]);
or o72(Q__7[1],0,Q_7[1]);
or o73(Q__7[2],0,Q_7[2]);
or o74(Q__7[3],0,Q_7[3]);
or o75(Q__7[4],0,Q_7[4]);
or o76(Q__7[5],0,Q_7[5]);
or o77(Q__7[6],0,Q_7[6]);
or o78(Q__7[7],0,Q_7[7]);

////////////////8 term/////////////////

wire [7:0] A_8;
wire [7:0] A__8;

wire [7:0] Q_8;
wire [7:0] Q__8;

wire [7:0] X_8;

wire [3:0] s_8; 	// 0 xnor
			// 1 xor
 			// 2 or 
			// 3 and

wire c_8;

left_shift l8({A__7,Q__7},{A_8,Q_8});

xnor x81(s_8[0],A_8[7],divisor[7]);

add_sub_8bit a8(X_8,c_8,A_8,divisor,s_8[0]);	//  module add_sub_8bit(out,cout,in1,in2,M);

xor x82(s_8[1],A_8[7],X_8[7]);

or x83(s_8[2],X_8[7],X_8[6],X_8[5],X_8[4],X_8[3],X_8[2],X_8[1],X_8[0]);

and x84(s_8[3],s_8[2],s_8[1]);

mux_2to1 m81(s_8[3],{A_8[0],X_8[0]},A__8[0]);	//module mux_2to1(s,in,out);s=0 -> in[0]  s=1 -> in[1]
mux_2to1 m82(s_8[3],{A_8[1],X_8[1]},A__8[1]);
mux_2to1 m83(s_8[3],{A_8[2],X_8[2]},A__8[2]);
mux_2to1 m84(s_8[3],{A_8[3],X_8[3]},A__8[3]);
mux_2to1 m85(s_8[3],{A_8[4],X_8[4]},A__8[4]);
mux_2to1 m86(s_8[3],{A_8[5],X_8[5]},A__8[5]);
mux_2to1 m87(s_8[3],{A_8[6],X_8[6]},A__8[6]);
mux_2to1 m88(s_8[3],{A_8[7],X_8[7]},A__8[7]);

not o81(Q__8[0],s_8[3]);
or o82(Q__8[1],0,Q_8[1]);
or o83(Q__8[2],0,Q_8[2]);
or o84(Q__8[3],0,Q_8[3]);
or o85(Q__8[4],0,Q_8[4]);
or o86(Q__8[5],0,Q_8[5]);
or o87(Q__8[6],0,Q_8[6]);
or o88(Q__8[7],0,Q_8[7]);



wire [7:0] oRe;
wire [7:0] oQu;


///////////////compare sign of dividend and divisor -> 2nd complement of Quotient

wire p;
wire s;

xor p0(s,iDividend[15],divisor[7]);

add_sub_8bit p1(oQu,p,0,Q__8,s); //module add_sub_8bit(out,cout,in1,in2,M);


/////////////////////////////////////////////////////////////////////////////////

assign oRe[7]=A__8[7];
assign oRe[6]=A__8[6];
assign oRe[5]=A__8[5];
assign oRe[4]=A__8[4];
assign oRe[3]=A__8[3];
assign oRe[2]=A__8[2];
assign oRe[1]=A__8[1];
assign oRe[0]=A__8[0];

register_8bit re(iClk,r,oRe,oReminder);
register_8bit qu(iClk,r,oQu,oQuotient);

wire [1:0] fi;

or finish(fi[0],oReminder[0],oReminder[1],oReminder[2],oReminder[3],oReminder[4],oReminder[5],oReminder[6],oReminder[7]);

and fin(fi[1],fi[0],r);
assign oDone=fi[1];

endmodule

module mux_2to1(s,in,out);

input s;
input [1:0] in;
output out;
wire a,b,c;

not q1(a,s);
and q2(b,in[0],a);
and q3(c,in[1],s);
or q4(out,b,c);  // s=0 -> in[0]  s=1 -> in[1]

endmodule

module left_shift(in,out);

input [15:0] in;
output [15:0] out;

or or1(out[0],0,0);
or or2(out[1],in[0],0);
or or3(out[2],in[1],0);
or or4(out[3],in[2],0);
or or5(out[4],in[3],0);
or or6(out[5],in[4],0);
or or7(out[6],in[5],0);
or or8(out[7],in[6],0);
or or9(out[8],in[7],0);
or or10(out[9],in[8],0);
or or11(out[10],in[9],0);
or or12(out[11],in[10],0);
or or13(out[12],in[11],0);
or or14(out[13],in[12],0);
or or15(out[14],in[13],0);
or or16(out[15],in[14],0);


endmodule

module full_adder(out,cout,in1,in2,cin);

input in1;
input in2;
input cin;
output out;
output cout;

wire w1,w2,w3;

xor t1(w1,in1,in2);
xor t2(out,w1,cin);
and t3(w2,in1,in2);
and t4(w3,w1,cin);
or  t6(cout,w2,w3);

endmodule


module add_sub_8bit(out,cout,in1,in2,M);

input [7:0] in1;
input [7:0] in2;
input M; //M=0 add M=1 sub

output [7:0] out;
output cout ;

wire [7:0] w1,w2;

xor x1(w1[0],M,in2[0]);
xor x2(w1[1],M,in2[1]);
xor x3(w1[2],M,in2[2]);
xor x4(w1[3],M,in2[3]);
xor x5(w1[4],M,in2[4]);
xor x6(w1[5],M,in2[5]);
xor x7(w1[6],M,in2[6]);
xor x8(w1[7],M,in2[7]);

full_adder f1(out[0],w2[0],in1[0],w1[0],M);
full_adder f2(out[1],w2[1],in1[1],w1[1],w2[0]);
full_adder f3(out[2],w2[2],in1[2],w1[2],w2[1]);
full_adder f4(out[3],w2[3],in1[3],w1[3],w2[2]);
full_adder f5(out[4],w2[4],in1[4],w1[4],w2[3]);
full_adder f6(out[5],w2[5],in1[5],w1[5],w2[4]);
full_adder f7(out[6],w2[6],in1[6],w1[6],w2[5]);
full_adder f8(out[7],w2[7],in1[7],w1[7],w2[6]);


endmodule

module dflipflop(
  clk,
  rst, 
  input1,
  output1,
  noutput1
);

input input1, clk, rst;
output output1, noutput1;

wire w1, w2, w3, w4;
wire  input2;
and a1(input2, input1, rst);

nand n1(w1, w4, w2);
nand n2(w2, w1, clk);
nand n3(w3, w2, clk, w4);
nand n4(w4, w3, input2);

nand n5(output1, w2, noutput1);
nand n6(noutput1, output1, w3);


endmodule

module register_8bit(clk,rst,d,q);

  input clk, rst;
  input [7:0]d;
  output [7:0]q;
  
  wire [7:0]nq;
  
  dflipflop d1(clk, rst, d[0], q[0], nq[0]);
  dflipflop d2(clk, rst, d[1], q[1], nq[1]);
  dflipflop d3(clk, rst, d[2], q[2], nq[2]);
  dflipflop d4(clk, rst, d[3], q[3], nq[3]);
  dflipflop d5(clk, rst, d[4], q[4], nq[4]);
  dflipflop d6(clk, rst, d[5], q[5], nq[5]);
  dflipflop d7(clk, rst, d[6], q[6], nq[6]);
  dflipflop d8(clk, rst, d[7], q[7], nq[7]);
  
endmodule
  
module register_16bit(clk,rst,d,q);
  
input clk, rst;
input [15:0]d;
output [15:0]q;

register_8bit er1(clk, rst, d[15:8], q[15:8]);
register_8bit er2(clk, rst, d[7:0], q[7:0]);

endmodule

module register_24bit(clk,rst,d,q);
  
input clk, rst;
input [23:0]d;
output [23:0]q;

register_8bit er1(clk, rst, d[23:16], q[23:16]);
register_8bit er2(clk, rst, d[15:8], q[15:8]);
register_8bit er3(clk, rst, d[7:0], q[7:0]);


endmodule

*/












